Signal Integrity by Samuel H. Russ

Author:Samuel H. Russ
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

Departures from the Ideal

A transmission line is a stable, easily fabricated structure that can carry signals well up into the 10s of GHz. The key to perfect signal integrity is for the transmission line structure to have a completely uniform cross section down its entire length.

So what causes departures from this ideal? Many things – including slots in the ground plane, vias (passages from one layer to another), right-angle bends or turns, and additional logic inputs in the middle of the line – can cause changes to the uniformity.

Most obstructions, such as vias, bends, and additional inputs, cause extra capacitance. A shunt capacitance lowers the Z 0 at the point where it connects to the line and so causes a small negative reflection. Since the capacitor has a derivative relationship between current and voltage, the reflection is the first derivative of the incoming waveform. For example, if the waveform is a rising edge, the reflection is a negative pulse.

These negative pulses can look like false logic transitions at inputs that are located nearer the source. Also, if load termination is used, the pulses can reflect off of the poorly terminated source and travel back out onto the line.

In the transmission direction, the combination of the capacitance and the Z 0 of the line actually creates an RC filter that slows the signal and increases the risetime. At the point the capacitor contacts the transmission line, the Z 0 of the upstream and downstream directions are in parallel, so the effective resistance “seen” by the capacitor is Z 0/2. The overall risetime adder is 2.2 * Z 0/2 * C = 1.1 Z 0 C. If the signal passes multiple capacitive loads (a common case on a bus), then the risetime steadily grows as the signal moves down the line (and a stream of negative pulses is sent back to the source).

A SPICE simulation of a capacitive imperfection is shown below in Fig. 6.8. The circuit in the simulation used source termination, so the initial reflection of the falling edge off of the capacitor is absorbed at the source. However, in source termination, there is a nearly total reflection off of the load. The load reflection actually reflects off of the capacitor and comes back to the load. Since the sign of the capacitor’s reflection coefficient is negative, the reflection of the falling edge is a rising spike. Since the sign is opposite, it can be mistaken by the load as an extra logic transition. The simulation also shows how the “reflection of the reflection” turns into a second-derivative double pulse.

Fig. 6.8Capacitor in the middle of line with source termination

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